This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
Integrated circuits (IC) may be formed from arrangements of one or more input/output devices, standard devices, memory devices, and/or the like. In one scenario, memory devices may include memory arrays arranged into memory cells and the associated circuitry to write data to the memory cells and read data from the memory cells. In particular, the memory cells of a memory array, such as a random access memory (RAM) array, may be organized into rows and columns. The logic latches within these individual memory cells may be used to store a data bit that is representative of a logical “1” or “0.” These memory cells may also be interconnected by word-lines (WL) and pairs of complementary bit-lines (BL).
A retention voltage in an integrated circuit can be used to hold components of that integrated circuit in a data retention state. For example, a memory device may be powered down as much as possible, where a retention voltage applied to memory cells of the memory device may be reduced to a level at which information stored therein can be maintained, and where that retention voltage may be kept as low as possible to avoid power consumption through current leakage. Given that the power consumption of such a device can be logarithmic with the voltage applied, an integrated circuit may be configured to provide as low a retention voltage as possible to the memory device.